Conventional SRAM architecture is used for on-chip quick memory access, such as with cache memories. Bit line drivers drive bit lines and word line drivers drive word lines connected to cells in the SRAM to read and write information from and to memory cells in the SRAM. When effectuating a read in such a system, a word line is energized to allow the bit lines access to connected memory cells. A pair of bit lines is pre-charged before energizing the word line. Subsequently, a voltage across the pair of bit lines, representative of the stored value, is read by a sense amplifier to effectuate the read operation. A latching circuit latches the amplified voltage and holds it available for devices to read. The word line is again charged to allow access to the desired cell in the array. Here, one bit line is charged while the other is not to effectuate the write to a cell.
In such architectures, managing power dissipation has become an increasingly important goal. To this end, some computing systems have begun to use recovery or adiabatic clock circuits to recycle the clock signal pulse that is sent across the bit lines and word lines, via the bit line drivers and the word line drivers, in an attempt to reduce power consumption. While this does effectuate energy savings, some drawbacks currently exist with the present state of this technology. Specifically, such systems are commonly complex and yield clock signal waveforms that either fail to provide energy recovery characteristics, such as an abrupt or square wave, or fail to provide needed switching capabilities. The present invention was developed in light of these and other drawbacks.